Comments on: ARM-NEON memory hazards http://hardwarebug.org/2008/12/31/arm-neon-memory-hazards/ Everything is broken Mon, 30 Aug 2010 09:33:38 +0000 hourly 1 http://wordpress.org/?v=3.0.1 By: Mans http://hardwarebug.org/2008/12/31/arm-neon-memory-hazards/comment-page-1/#comment-1132 Mans Wed, 30 Jun 2010 21:54:35 +0000 http://hardwarebug.org/?p=89#comment-1132 You, or your OS, are obviously doing something wrong. That code should work. You, or your OS, are obviously doing something wrong. That code should work.

]]> By: Brett http://hardwarebug.org/2008/12/31/arm-neon-memory-hazards/comment-page-1/#comment-1131 Brett Tue, 29 Jun 2010 20:58:18 +0000 http://hardwarebug.org/?p=89#comment-1131 Have you seen any issues with vld and registers q8-15? For some reason, doing a load to registers below q8 work fine, but above q8 the registers don't get set. For example, the first won't work but the second will. <pre> vld1.32 {d16-d17}, [r3] vld1.32 {d0-d1}, [r3] </pre> any ideas? Have you seen any issues with vld and registers q8-15?

For some reason, doing a load to registers below q8 work fine, but above q8 the registers don’t get set.

For example, the first won’t work but the second will.

vld1.32	{d16-d17}, [r3]
vld1.32	{d0-d1}, [r3]

any ideas?

]]> By: Mans http://hardwarebug.org/2008/12/31/arm-neon-memory-hazards/comment-page-1/#comment-1127 Mans Thu, 24 Jun 2010 20:52:03 +0000 http://hardwarebug.org/?p=89#comment-1127 The purpose of this investigation was to determine the undocumented memory hazards. Instruction latencies are well-documented in the TRM. The purpose of this investigation was to determine the undocumented memory hazards. Instruction latencies are well-documented in the TRM.

]]> By: cf http://hardwarebug.org/2008/12/31/arm-neon-memory-hazards/comment-page-1/#comment-1126 cf Thu, 24 Jun 2010 20:20:01 +0000 http://hardwarebug.org/?p=89#comment-1126 You're forgetting 1 very important hazard - the SIMD ones that cause NEON pipeline stalls. If you try to access the result of one NEON operation before the operation is complete, then the NEON pipeline will stall until the result is ready. You’re forgetting 1 very important hazard – the SIMD ones that cause NEON pipeline stalls. If you try to access the result of one NEON operation before the operation is complete, then the NEON pipeline will stall until the result is ready.

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