Comments on: ARM-NEON memory hazards

By: Shervin Emami

Shervin Emami — Fri, 24 Sep 2010 05:31:53 +0000

You say at the end “It should also be noted that in all other cases, the 64-bit store is faster.”

Did you mean 64-bit or 64-byte? Also, could you please explain a little bit more about what your 16-byte, 64-byte and Other columns represent? Does it mean that ARM loads should be spaced atleast 64-bytes after NEON stores?

By: Mans

Mans — Wed, 30 Jun 2010 21:54:35 +0000

You, or your OS, are obviously doing something wrong. That code should work.

By: Brett

Brett — Tue, 29 Jun 2010 20:58:18 +0000

Have you seen any issues with vld and registers q8-15?

For some reason, doing a load to registers below q8 work fine, but above q8 the registers don’t get set.

For example, the first won’t work but the second will.

vld1.32	{d16-d17}, [r3]
vld1.32	{d0-d1}, [r3]

any ideas?

By: Mans

Mans — Thu, 24 Jun 2010 20:52:03 +0000

The purpose of this investigation was to determine the undocumented memory hazards. Instruction latencies are well-documented in the TRM.

By: cf

cf — Thu, 24 Jun 2010 20:20:01 +0000

You’re forgetting 1 very important hazard – the SIMD ones that cause NEON pipeline stalls. If you try to access the result of one NEON operation before the operation is complete, then the NEON pipeline will stall until the result is ready.